Saeideh Shirinzadeh
Saeideh Shirinzadeh
Verified email at uni-bremen.de
Title
Cited by
Cited by
Year
Fast logic synthesis for RRAM-based in-memory computing using majority-inverter graphs
S Shirinzadeh, M Soeken, PE Gaillardon, R Drechsler
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 948-953, 2016
562016
An MIG-based compiler for programmable logic-in-memory architectures
M Soeken, S Shirinzadeh, PE Gaillardon, LG Amarú, R Drechsler, ...
2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2016
312016
Logic synthesis for RRAM-based in-memory computing
S Shirinzadeh, M Soeken, PE Gaillardon, R Drechsler
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017
302017
Time-resolved detection of diffusion limited temperature gradients inside single isolated burning droplets using Rainbow Refractometry
CD Rosebrock, S Shirinzadeh, M Soeken, N Riefler, T Wriedt, R Drechsler, ...
Combustion and Flame 168, 255-269, 2016
282016
A novel soft error hardened latch design in 90nm CMOS
S Shirinzadeh, RN Asli
The 16th CSI International Symposium on Computer Architecture and Digital …, 2012
172012
Multi-objective BDD optimization for RRAM based circuit design
S Shirinzadeh, M Soeken, R Drechsler
2016 IEEE 19th International Symposium on Design and Diagnostics of …, 2016
162016
A PLiM computer for the internet of things
M Soeken, PE Gaillardon, S Shirinzadeh, R Drechsler, G De Micheli
Computer 50 (6), 35-40, 2017
132017
Multi-objective BDD optimization with evolutionary algorithms
S Shirinzadeh, M Soeken, R Drechsler
Proceedings of the 2015 Annual Conference on Genetic and Evolutionary …, 2015
122015
Endurance management for resistive logic-in-memory computing architectures
S Shirinzadeh, M Soeken, PE Gaillardon, G De Micheli, R Drechsler
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017
112017
Design and performance evaluation of a low cost full protected CMOS latch
S Shirinzadeh, RN Asli
The 17th CSI International Symposium on Computer Architecture & Digital …, 2013
112013
High efficiency time redundant hardened latch for reliable circuit design
RN Asli, S Shirinzadeh
Journal of Electronic Testing 29 (4), 537-544, 2013
102013
Logic synthesis for majority based in-memory computing
S Shirinzadeh, M Soeken, PE Gaillardon, R Drechsler
Advances in Memristors, Memristive Devices and Systems, 425-448, 2017
72017
Synthesis of optical circuits using binary decision diagrams
A Deb, R Wille, O Keszöcze, S Shirinzadeh, R Drechsler
Integration 59, 42-51, 2017
62017
Approximate BDD optimization with prioritized ε-preferred evolutionary algorithm
S Shirinzadeh, M Soeken, D Große, R Drechsler
Proceedings of the 2016 on Genetic and Evolutionary Computation Conference …, 2016
52016
Logic synthesis for in-memory computing using resistive memories
S Shirinzadeh, R Drechsler
2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 375-380, 2018
42018
Logic design using memristors: An emerging technology
S Shirinzadeh, K Datta, R Drechsler
2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL), 121-126, 2018
42018
An adaptive prioritized ε-preferred evolutionary algorithm for approximate BDD optimization
S Shirinzadeh, M Soeken, D Große, R Drechsler
Proceedings of the Genetic and Evolutionary Computation Conference, 1232-1239, 2017
42017
In-Memory Computing: The Integration of Storage and Processing
S Shirinzadeh, R Drechsler
Information Storage, 79-110, 2020
32020
Synthesis for Logic-in-Memory Computing Using RRAM
S Shirinzadeh, R Drechsler
In-Memory Computing, 49-81, 2020
12020
Comprime: A compiler for parallel and scalable reram-based in-memory computing
S Frerix, S Shirinzadeh, S Fröhlich, R Drechsler
2019 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), 1-6, 2019
12019
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