Bi-synchronous FIFO for synchronous circuit communication well suited for network-on-chip in GALS architectures IM Panades, A Greiner
First International Symposium on Networks-on-Chip (NOCS'07), 83-94, 2007
155 2007 A low cost network-on-chip with guaranteed service well suited to the GALS approach IM Panades, A Greiner, A Sheibanyrad
2006 1st International Conference on Nano-Networks and Workshops, 1-5, 2006
139 2006 A 477mW NoC-Based Digital Baseband for MIMO 4G SDR F Clermidy, C Bernard, R Lemaire, J Martin, I Miro-Panades, Y Thonnart, ...
125 2010 Multisynchronous and fully asynchronous NoCs for GALS architectures A Sheibanyrad, A Greiner, I Miro-Panades
IEEE Design & Test of Computers 25 (6), 572-580, 2008
86 2008 Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture I Miro-Panades, F Clermidy, P Vivet, A Greiner
Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008), 139-148, 2008
75 2008 Energy-efficient near-threshold parallel computing: The PULPv2 cluster D Rossi, A Pullini, I Loi, M Gautschi, FK Gürkaynak, A Teman, ...
Ieee Micro 37 (5), 20-31, 2017
70 2017 IntAct: A 96-core processor with six chiplets 3D-stacked on an active interposer with distributed interconnects and integrated power management P Vivet, E Guthmuller, Y Thonnart, G Pillonnet, C Fuguet, I Miro-Panades, ...
IEEE Journal of Solid-State Circuits 56 (1), 79-97, 2020
68 2020 2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm … P Vivet, E Guthmuller, Y Thonnart, G Pillonnet, G Moritz, I Miro-Panadès, ...
2020 IEEE International Solid-State Circuits Conference-(ISSCC), 46-48, 2020
64 2020 A 460 mhz at 397 mv, 2.6 ghz at 1.3 v, 32 bits vliw dsp embedding f max tracking E Beigne, A Valentian, I Miro-Panades, R Wilson, P Flatresse, F Abouzeid, ...
IEEE Journal of Solid-State Circuits 50 (1), 125-136, 2014
60 2014 A Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links P Vivet, Y Thonnart, R Lemaire, C Santos, E Beigné, C Bernard, F Darve, ...
IEEE Journal of Solid-State Circuits 52 (1), 33-49, 2016
57 2016 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking R Wilson, E Beigne, P Flatresse, A Valentian, F Abouzeid, T Benoist, ...
2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014
52 2014 Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture A Sheibanyrad, IM Panades, A Greiner
2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007
48 2007 193 MOPS/mW@ 162 MOPS, 0.32 V to 1.15 V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing D Rossi, A Pullini, I Loi, M Gautschi, FK Gurkaynak, A Teman, ...
2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX), 1-3, 2016
47 2016 A Fine-Grain Variation-Aware Dynamic -Hopping AVFS Architecture on a 32 nm GALS MPSoC I Miro-Panades, E Beigné, Y Thonnart, L Alacoque, P Vivet, S Lesecq, ...
IEEE Journal of Solid-State Circuits 49 (7), 1475-1486, 2014
35 2014 SamurAI: A 1.7 MOPS-36GOPS adaptive versatile IoT node with 15,000× peak-to-idle power reduction, 207ns wake-up time and 1.3 TOPS/W ML efficiency I Miro-Panades, B Tain, JF Christmann, D Coriat, R Lemaire, C Jany, ...
2020 IEEE Symposium on VLSI Circuits, 1-2, 2020
32 2020 MAGALI: A Network-on-Chip based multi-core system-on-chip for MIMO 4G SDR F Clermidy, C Bernard, R Lemaire, J Martin, I Miro-Panades, Y Thonnart, ...
2010 IEEE International Conference on Integrated Circuit Design and …, 2010
28 2010 Power management through DVFS and dynamic body biasing in FD-SOI circuits Y Akgul, D Puschini, S Lesecq, E Beigné, I Miro-Panades, P Benoit, ...
Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014
26 2014 3D advanced integration technology for heterogeneous systems P Vivet, C Bernard, F Clermidy, D Dutoit, E Guthmuller, IM Panadès, ...
2015 International 3D Systems Integration Conference (3DIC), FS6. 1-FS6. 3, 2015
20 2015 A 32 kb 0.35–1.2 V, 50 MHz–2.5 GHz bit-interleaved SRAM with 8 T SRAM cell and data dependent write assist in 28-nm UTBB-FDSOI CMOS A Grover, GS Visweswaran, CR Parthasarathy, M Daud, D Turgis, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 64 (9), 2438-2447, 2017
19 2017 Architecture and robust control of a digital frequency-locked loop for fine-grain dynamic voltage and frequency scaling in globally asynchronous locally synchronous structures C Albea, D Puschini, P Vivet, I Miro-Panades, E Beigné, S Lesecq
Journal of Low Power Electronics 7 (3), 328-340, 2011
19 2011