High-Level Synthesis of Dynamic Data Structures: A Case Study Using Vivado HLS F Winterstein, S Bayliss, GA Constantinides International Conference on Field-Programmable Technology (FPT), 362 - 365, 2013 | 157 | 2013 |
FPGA-based K-means clustering using tree-based data structures F Winterstein, S Bayliss, GA Constantinides 2013 23rd International Conference on Field programmable Logic and …, 2013 | 69 | 2013 |
A case for work-stealing on FPGAs with OpenCL atomics N Ramanathan, J Wickerson, F Winterstein, GA Constantinides Proceedings of the 2016 ACM/SIGDA International Symposium on Field …, 2016 | 44 | 2016 |
MATCHUP: Memory abstractions for heap manipulating programs F Winterstein, K Fleming, HJ Yang, S Bayliss, G Constantinides Proceedings of the 2015 ACM/SIGDA International Symposium on Field …, 2015 | 42 | 2015 |
Separation Logic-Assisted Code Transformations for Efficient High-Level Synthesis F Winterstein, S Bayliss, G Constantinides IEEE 22nd Annual International Symposium on Field-Programmable Custom …, 2014 | 23 | 2014 |
Custom-sized caches in application-specific memory hierarchies F Winterstein, K Fleming, HJ Yang, J Wickerson, G Constantinides 2015 International Conference on Field Programmable Technology (FPT), 144-151, 2015 | 17 | 2015 |
Pass a pointer: Exploring shared virtual memory abstractions in OpenCL tools for FPGAs F Winterstein, G Constantinides 2017 International Conference on Field Programmable Technology (ICFPT), 104-111, 2017 | 14 | 2017 |
Separation logic for high-level synthesis FJ Winterstein, SR Bayliss, GA Constantinides ACM Transactions on Reconfigurable Technology and Systems (TRETS) 9 (2), 1-23, 2015 | 13 | 2015 |
Scavenger: Automating the construction of application-optimized memory hierarchies HJ Yang, K Fleming, M Adler, F Winterstein, J Emer 2015 25th International Conference on Field Programmable Logic and …, 2015 | 12 | 2015 |
Automatic construction of program-optimized FPGA memory networks HJ Yang, K Fleming, F Winterstein, AI Chen, M Adler, J Emer Proceedings of the 2017 ACM/SIGDA International Symposium on Field …, 2017 | 8 | 2017 |
LMC: Automatic resource-aware program-optimized memory partitioning HJ Yang, K Fleming, M Adler, F Winterstein, J Emer Proceedings of the 2016 ACM/SIGDA International Symposium on Field …, 2016 | 8 | 2016 |
Separation Logic for High-level Synthesis F Winterstein Springer, 2017 | 6 | 2017 |
Custom multicache architectures for heap manipulating programs F Winterstein, KE Fleming, HJ Yang, GA Constantinides IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2016 | 3 | 2016 |
Compiling higher order functional programs to composable digital hardware E Aguilar-Pelaez, S Bayliss, A Smith, F Winterstein, DR Ghica, D Thomas, ... 2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom …, 2014 | 3 | 2014 |
(FPL 2015) Scavenger: Automating the Construction of Application-Optimized Memory Hierarchies HJ Yang, K Fleming, F Winterstein, M Adler, J Emer ACM Transactions on Reconfigurable Technology and Systems (TRETS) 10 (2), 1-23, 2017 | 2 | 2017 |
High-level synthesis of dynamic data structures F Winterstein, F Winterstein Separation Logic for High-level Synthesis, 11-33, 2017 | 2 | 2017 |
A power-aware adaptive FDIR framework using heterogeneous system-on-chip modules ST Fleming, DB Thomas, F Winterstein FPGAs and Parallel Architectures for Aerospace Applications: Soft Errors and …, 2016 | 2 | 2016 |
Scalable front-end digital signal processing for a phased array radar demonstrator F Winterstein, G Sessler, M Montagna, M Mendijur, G Dauron, P Besso 2012 13th International Radar Symposium, 177-182, 2012 | 1 | 2012 |
Design and implementation of a low power mini-radar demonstrator G Sessler, M Martinez, M Montagna, A Martin, F Winterstein, G Dauron, ... Proc. European Space Surveillance Conference (ESSC) 2011, 2011 | 1 | 2011 |
Custom Multi-cache Architectures F Winterstein, F Winterstein Separation Logic for High-level Synthesis, 85-115, 2017 | | 2017 |