Pasquale Davide Schiavone
Pasquale Davide Schiavone
EPFL, OpenHW Group
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Near-threshold RISC-V core with DSP extensions for scalable IoT endpoint devices
M Gautschi, PD Schiavone, A Traber, I Loi, A Pullini, D Rossi, E Flamand, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (10 …, 2017
Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications
PD Schiavone, F Conti, D Rossi, M Gautschi, A Pullini, E Flamand, ...
2017 27th International Symposium on Power and Timing Modeling, Optimization …, 2017
An IoT endpoint system-on-chip for secure and energy-efficient near-sensor analytics
F Conti, R Schilling, PD Schiavone, A Pullini, D Rossi, FK Gürkaynak, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 64 (9), 2481-2494, 2017
XNOR neural engine: A hardware accelerator IP for 21.6-fJ/op binary neural network inference
F Conti, PD Schiavone, L Benini
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
A sensor fusion approach for drowsiness detection in wearable ultra-low-power systems
VJ Kartsch, S Benatti, PD Schiavone, D Rossi, L Benini
Information Fusion 43, 66-76, 2018
Fast and accurate multiclass inference for MI-BCIs using large multiscale temporal and spectral features
M Hersche, T Rellstab, PD Schiavone, L Cavigelli, L Benini, A Rahimi
2018 26th European Signal Processing Conference (EUSIPCO), 1690-1694, 2018
Quentin: an ultra-low-power pulpissimo soc in 22nm fdx
PD Schiavone, D Rossi, A Pullini, A Di Mauro, F Conti, L Benini
2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2018
Always-on 674μ W@ 4GOP/s error resilient binary neural networks with aggressive SRAM voltage scaling on a 22-nm IoT end-node
A Di Mauro, F Conti, PD Schiavone, D Rossi, L Benini
IEEE Transactions on Circuits and Systems I: Regular Papers 67 (11), 3905-3918, 2020
An evolutionary approach for test program compaction
R Cantoro, M Gaudesi, E Sanchez, PD Schiavone, G Squillero
2015 16th Latin-American Test Symposium (LATS), 2015
Arnold: An eFPGA-augmented RISC-V SoC for flexible and low-power IoT end nodes
PD Schiavone, D Rossi, A Di Mauro, FK Gürkaynak, T Saxe, M Wang, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (4), 677-690, 2021
RI5CY: User manual
A Traber, M Gautschi, PD Schiavone
Micrel Lab Multitherman Lab, Univ. Bologna, Italy. Integr. Syst. Lab, ETH …, 2019
An open-source verification framework for open-source cores: A RISC-V case study
PD Schiavone, E Sanchez, A Ruospo, F Minervini, F Zaruba, G Haugou, ...
2018 IFIP/IEEE International Conference on Very Large Scale Integration …, 2018
On-line testing for autonomous systems driven by RISC-V processor design verification
A Ruospo, R Cantoro, E Sanchez, PD Schiavone, A Garofalo, L Benini
2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2019
Pushing on-chip memories beyond reliability boundaries in micropower machine learning applications
A Di Mauro, F Conti, PD Schiavone, D Rossi, L Benini
2019 IEEE International Electron Devices Meeting (IEDM), 30.4. 1-30.4. 4, 2019
HW/SW approaches for RISC-V code size reduction
M Perotti, PD Schiavone, G Tagliavini, D Rossi, T Kurd, M Hill, L Yingying, ...
Workshop on Computer Architecture Research with RISC-V (CARRV 2020), 2020
Tiny-FPU: low-cost floating-point support for small RISC-V MCU cores
L Bertaccini, M Perotti, S Mach, PD Schiavone, F Zaruba, L Benini
2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2021
Neuro-PULP: a paradigm shift towards fully programmable platforms for neural interfaces
PD Schiavone, D Rossi, Y Liu, S Benatti, S Luan, I Williams, L Benini, ...
2020 2nd IEEE International Conference on Artificial Intelligence Circuits …, 2020
KISS PULPino-Updates on PULPino: updates on PULPino
A Pullini, M Gautschi, FK Gürkaynak, F Glaser, S Mach, G Rovere, ...
5th RISC-V Workshop, 2016
sEMG Neural Spikes Reconstruction for Gesture Recognition on a Low-Power Multicore Processor
M Orlandi, M Zanghieri, VJK Morinigo, F Conti, D Schiavone, L Benini, ...
2022 IEEE Biomedical Circuits and Systems Conference (BioCAS), 704-708, 2022
Motor-Unit Ordering of Blindly-Separated Surface-EMG Signals for Gesture Recognition
M Orlandi, M Zanghieri, D Schiavone, E Donati, F Conti, S Benatti
Advances in System-Integrated Intelligence: Proceedings of the 6th …, 2022
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