Andrea Calimera
Andrea Calimera
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The human brain project and neuromorphic computing
A Calimera, E Macii, M Poncino
Funct Neurol 28 (3), 191-196, 2013
1022013
NBTI-aware power gating for concurrent leakage and aging optimization
A Calimera, E Macii, M Poncino
Proceedings of the 14th ACM/IEEE international symposium on Low power …, 2009
1022009
Design techniques for NBTI-tolerant power-gating architectures
A Calimera, E Macii, M Poncino
IEEE Transactions on Circuits and Systems II: Express Briefs 59 (4), 249-253, 2012
862012
Design techniques and architectures for low-leakage SRAMs
A Calimera, A Macii, E Macii, M Poncino
IEEE Transactions on Circuits and Systems I: Regular Papers 59 (9), 1992-2007, 2012
692012
Enabling concurrent clock and power gating in an industrial design flow
L Bolzani, A Calimera, A Macii, E Macii, M Poncino
Proceedings of the Conference on Design, Automation and Test in Europe, 334-339, 2009
522009
NBTI-Aware Clustered Power Gating
A Calimera, E Macii, M Poncino
ACM Transactions on Design Automation of Electronic Systems (TODAES) 16 (1 …, 2010
402010
Integrating clock gating and power gating for combined dynamic and leakage power optimization in digital cmos circuits
E Macii, L Bolzani, A Calimera, A Macii, M Poncino
Digital System Design Architectures, Methods and Tools, 2008. DSD'08. 11th …, 2008
352008
Design of a flexible reactivation cell for safe power-mode transition in power-gated circuits
A Calimera, L Benini, A Macii, E Macii, M Poncino
Circuits and Systems I: Regular Papers, IEEE Transactions on 56 (9), 1979-1993, 2009
342009
NBTI-aware sleep transistor design for reliable power-gating
A Calimera, E Macii, M Poncino
Proceedings of the 19th ACM Great Lakes symposium on VLSI, 333-338, 2009
342009
Analysis of NBTI-induced SNM degradation in power-gated SRAM cells
A Calimera, E Macii, M Poncino
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International …, 2010
332010
NBTI-aware data allocation strategies for scratchpad based embedded systems
C Ferri, D Papagiannopoulou, RI Bahar, A Calimera
Test Workshop (LATW), 2011 12th Latin American, 1-6, 2011
29*2011
NBTI-Aware Data Allocation Strategies for Scratchpad Memory Based Embedded Systems
C Ferri, D Papagiannopoulou, I Bahar, A Calimera
28*
Partitioned cache architectures for reduced NBTI-induced aging
A Calimera, M Loghi, E Macii, M Poncino
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011, 1-6, 2011
252011
Dynamic indexing: concurrent leakage and aging optimization for caches
A Calimera, M Loghi, E Macii, M Poncino
Proceedings of the 16th ACM/IEEE international symposium on Low power …, 2010
252010
Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits
A Calimera, RI Bahar, E Macii, M Poncino
Proceeding of the 13th international symposium on Low power electronics and …, 2008
252008
Temperature-insensitive synthesis using multi-vt libraries
A Calimera, E Macii, M Poncino, R Bahar
Proceedings of the 18th ACM Great Lakes symposium on VLSI, 5-10, 2008
242008
Temperature-Insensitive Dual-Vth Synthesis for Nanometer CMOS Technologies Under Inverse Temperature Dependence
A Calimera, RI Bahar, E Macii, M Poncino
IEEE transactions on very large scale integration (VLSI) systems 18 (11), 1608, 2010
222010
Efficient computation of discharge current upper bounds for clustered sleep transistor sizing
A Sathanur, A Calimera, L Benini, A Macii, E Macii, M Poncino
2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007
22*2007
Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology
A Calimera, A Pullini, AV Sathanur, L Benini, A Macii, E Macii, M Poncino
Proceedings of the 17th ACM Great Lakes symposium on VLSI, 501-504, 2007
212007
A verilog-a model for reconfigurable logic gates based on graphene pn-junctions
S Miryala, M Montazeri, A Calimera, E Macii, M Poncino
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 877-880, 2013
162013
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