| A 0.5-to-2.5 Gb/s reference-less half-rate digital CDR with unlimited frequency acquisition range and improved input duty-cycle error tolerance R Inti, W Yin, A Elshazly, N Sasidhar, PK Hanumolu IEEE Journal of Solid-State Circuits 46 (12), 3150-3162, 2011 | 114 | 2011 |
| A 71dB SFDR open loop VCO-based ADC using 2-level PWM modulation S Rao, B Young, A Elshazly, W Yin, N Sasidhar, PK Hanumolu 2011 Symposium on VLSI Circuits-Digest of Technical Papers, 270-271, 2011 | 110 | 2011 |
| A 0.7-to-3.5 GHz 0.6-to-2.8 mW highly digital phase-locked loop with bandwidth tracking W Yin, R Inti, A Elshazly, B Young, PK Hanumolu IEEE Journal of Solid-State Circuits 46 (8), 1870-1880, 2011 | 85 | 2011 |
| A 0.4-to-3 GHz digital PLL with PVT insensitive supply noise cancellation using deterministic background calibration A Elshazly, R Inti, W Yin, B Young, PK Hanumolu IEEE journal of solid-state circuits 46 (12), 2759-2771, 2011 | 45 | 2011 |
| A high-speed high-resolution low-distortion CMOS bootstrapped switch L Wang, J Ren, W Yin, T Chen, J Xu 2007 IEEE International Symposium on Circuits and Systems, 1721-1724, 2007 | 42 | 2007 |
| A highly digital 0.5-to-4Gb/s 1.9 mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS R Inti, A Elshazly, B Young, W Yin, M Kossel, T Toifl, PK Hanumolu 2011 IEEE International Solid-State Circuits Conference, 152-154, 2011 | 41 | 2011 |
| A TDC-less 7 mW 2.5 Gb/s digital CDR with linear loop dynamics and offset-free data recovery W Yin, R Inti, A Elshazly, M Talegaonkar, B Young, PK Hanumolu IEEE journal of solid-state circuits 46 (12), 3163-3173, 2011 | 37 | 2011 |
| A 0.4-to-3GHz digital PLL with supply-noise cancellation using deterministic background calibration A Elshazly, R Inti, W Yin, B Young, PK Hanumolu 2011 IEEE International Solid-State Circuits Conference, 92-94, 2011 | 32 | 2011 |
| Phase-locked loop YIN Wenjing, A Gopalan US Patent 8,878,614, 2014 | 29 | 2014 |
| Dual-channel bootstrapped switch for high-speed high-resolution sampling L Wang, WJ Yin, J Xu, JY Ren Electronics Letters 42 (22), 1275 - 1276, 2006 | 21 | 2006 |
| A 1.6 mW 1.6 ps-rms-Jitter 2.5 GHz digital PLL with 0.7-to-3.5 GHz frequency range in 90nm CMOS W Yin, R Inti, PK Hanumolu IEEE Custom Integrated Circuits Conference 2010, 1-4, 2010 | 20 | 2010 |
| An undersampling 10-bit 30.4-MSample/s pipelined ADC W Yin, J Jiang, J Xu, F Ye, J Ren 2006 IEEE Asian Solid-State Circuits Conference, 343-346, 2006 | 7 | 2006 |
| Design techniques for high-performance digital PLLs and CDRs W Yin Oregon State University, 2011 | 2 | 2011 |
| A 8-bit 125-MSample/s pipelined ADC M Fan, T Chen, W Yin, L Wang, N Li, J Ren 2007 7th International Conference on ASIC, 585-587, 2007 | | 2007 |
| A self-control structure for pipeline control M Fan, T Chen, W Yin, L Wang, N Li, J Ren 2007 7th International Conference on ASIC, 24-27, 2007 | | 2007 |
| A bootstrapped sampling circuit for high-resolution and high-speed A/D converter. L Wang, WJ Yin, J Xu, JY Ren Weidianzixue(Microelectronics) 37 (1), 80-84, 2007 | | 2007 |
| ISSCC 2011/SESSION 8/ARCHITECTURES & CIRCUITS FOR NEXT GENERATION WIRELINE TRANSCEIVERS/8.6 R Inti, A Elshazly, B Young, W Yin, M Kossel, T Toifl, PK Hanumolu | | |
| ISSCC 2011/SESSION 25/CDRs & EQUALIZATION TECHNIQUES/25.3 W Yin, R Inti, A Elshazly, PK Hanumolu | | |
