Evanthia Papadopoulou
Evanthia Papadopoulou
Faculty of Informatics, Universitą della Svizzera italiana, Lugano, Switzerland
Verified email at usi.ch
Title
Cited by
Cited by
Year
Handbook of algorithms for physical design automation
CJ Alpert, DP Mehta, SS Sapatnekar
CRC press, 2008
2432008
The all-pairs quickest path problem
DT Lee, E Papadopoulou
Information Processing Letters 45 (5), 261-267, 1993
1011993
Method and system for determining critical area for circuit layouts
E Papadopoulou
US Patent 6,317,859, 2001
952001
Critical area computation via Voronoi diagrams
E Papadopoulou, DT Lee
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1999
861999
Incremental method for critical area and critical region computation of via blocks
E Papadopoulou, MA Lavin, GE Tellez, AJ Allen
US Patent 6,247,853, 2001
742001
THE L VORONOI DIAGRAM OF SEGMENTS AND VLSI APPLICATIONS
E Papadopoulou, DT Lee
International Journal of Computational Geometry & Applications 11 (05), 503-528, 2001
712001
Critical area computation for missing material defects in VLSI circuits
E Papadopoulou
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2001
662001
Method and system for determining critical area for circuit layouts using voronoi diagrams
E Papadopoulou, DT Lee
US Patent 6,178,539, 2001
522001
A new approach for the geodesic Voronoi diagram of points in a simple polygon and other restricted polygonal domains
E Papadopoulou, DT Lee
Algorithmica 20 (4), 319-352, 1998
491998
The Hausdorff Voronoi diagram of point clusters in the plane
E Papadopoulou
Algorithmica 40 (2), 63-82, 2004
432004
Voronoi diagrams for direction-sensitive distances
O Aichholzer, DZ Chen, DT Lee, A Mukhopadhyay, E Papadopoulou, ...
Proceedings of the thirteenth annual symposium on Computational geometry …, 1997
391997
Skew Voronoi diagrams
O Aichholzer, F Aurenhammer, DZ Chen, DT Lee, E Papadopoulou
International Journal of Computational Geometry & Applications 9 (03), 235-247, 1999
381999
Net-aware critical area extraction for opens in VLSI circuits via higher-order Voronoi diagrams
E Papadopoulou
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2011
372011
Yield Analysis and Optimization.
P Gupta, E Papadopoulou
Handbook of Algorithms for Physical Design Automation, 771-790, 2008
372008
The Hausdorff Voronoi diagram of polygonal objects: A divide and conquer approach
E Papadopoulou, DT Lee
International Journal of Computational Geometry & Applications 14 (06), 421-452, 2004
362004
Incremental critical area computation for VLSI yield prediction
E Papadopoulou, MA Lavin
US Patent 6,044,208, 2000
282000
IC design modeling allowing dimension-dependent rule checking
E Papadopoulou, DN Maynard
US Patent 7,404,164, 2008
262008
The higher-order Voronoi diagram of line segments
E Papadopoulou, M Zavershynskyi
Algorithmica 74 (1), 415-439, 2016
202016
On the farthest line-segment Voronoi diagram
E Papadopoulou, SK Dey
International Journal of Computational Geometry & Applications 23 (06), 443-459, 2013
192013
On the complexity of higher order abstract Voronoi diagrams
C Bohler, P Cheilaris, R Klein, CH Liu, E Papadopoulou, M Zavershynskyi
Computational Geometry 48 (8), 539-551, 2015
162015
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