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NITISH KUMAR
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Modeling the threshold voltage of core-and-outer gates of ultra-thin nanotube Junctionless-double gate-all-around (NJL-DGAA) MOSFETs
N Kumar, V Purwar, H Awasthi, R Gupta, K Singh, S Dubey
Microelectronics Journal 113, 105104, 2021
262021
A novel approach to model threshold voltage and subthreshold current of graded-doped junctionless-gate-all-around (GD-JL-GAA) MOSFETs
V Gupta, H Awasthi, N Kumar, AK Pandey, A Gupta
Silicon, 1-9, 2021
142021
A Novel Approach to Investigate the Impact of Hetero-High-K Gate Stack on SiGe Junctionless Gate-All-Around (JL-GAA) MOSFET
A Gupta, S Rai, N Kumar, D Sigroha, A Kishore, V Pathak, ZU Rahman
Silicon, 1-8, 2021
132021
Impact of temperature variation on analog, hot-carrier injection and linearity parameters of nanotube junctionless double-gate-all-around (NJL-DGAA) MOSFETs
N Kumar, H Awasthi, V Purwar, A Gupta, S Dubey
Silicon 14 (6), 2679-2686, 2022
122022
Impact of temperature on analog/RF performance of dielectric pocket gate-all-around (DPGAA) MOSFETs
H Awasthi, N Kumar, V Purwar, R Gupta, S Dubey
Silicon 13 (7), 2071-2075, 2021
112021
Investigating linearity and effect of temperature variation on analog/RF performance of dielectric pocket high-k double gate-all-around (DP-DGAA) MOSFETs
V Purwar, R Gupta, N Kumar, H Awasthi, VK Dixit, K Singh, S Dubey, ...
Applied Physics A 126, 1-8, 2020
92020
Thermal conductivity model to analyze the thermal implications in nanowire FETs
N Kumar, PK Kaushik, S Kumar, A Gupta, P Singh
IEEE Transactions on Electron Devices 69 (11), 6388-6393, 2022
82022
Impact of ambient temperature and thermal resistance on device performance of junctionless silicon-nanotube FET
N Kumar, PK Kaushik, A Gupta, P Singh
Nanotechnology 33 (33), 335201, 2022
82022
Temperature-dependent analytical modeling of graded-channel gate-all-around (GC-GAA) junctionless field-effect transistors (JLFETs)
V Gupta, N Kumar, H Awasthi, S Rai, AK Pandey, A Gupta
Journal of Electronic Materials 50, 3686-3691, 2021
52021
An analysis of Si-tube based double-material double gate-all-around (DMDGAA) MOSFEts. ICE3.(2020)
N Kumar, H Awasthi, V Purwar, A Gupta, A Gupta
5
Electro-thermal characteristics of junctionless nanowire gate-all-around transistors using compact thermal conductivity model
N Kumar, S Kumar, PK Kaushik, A Gupta, P Singh
IEEE Transactions on Electron Devices, 2023
42023
Simulation-based study of current gain peaks h 21 at low gate bias in AlGaN/GaN HEMTs
PK Kaushik, S Awasthi, N Kumar, U Goyal, M Mishra, A Gupta, A Basu
Engineering Research Express 4 (2), 025042, 2022
32022
Self-heating effects (SHEs) in gate-all-around FETs with horizontally stacked multiple junctionless nanowires
N Kumar, PK Kaushik, A Gupta, P Singh
2022 IEEE Delhi Section Conference (DELCON), 1-4, 2022
32022
Self-Heating Mapping of the Experimental Device and Its Optimization in Advance Sub-5nm Node Junctionless Multi-Nanowire FETs
N Kumar, S Pali, A Gupta, P Singh
IEEE Transactions on Device and Materials Reliability, 2023
22023
Drain extended MOS body region engineering for switching reliability under unclamped inductive load conditions
S Pali, N Kumar, A Gupta
IEEE Transactions on Device and Materials Reliability 23 (1), 134-141, 2023
22023
An analysis of Si-tube based double-material double gate-all-around (DMDGAA) MOSFETs
N Kumar, H Awasthi, V Purwar, A Gupta, A Gupta
2020 International Conference on Electrical and Electronics Engineering …, 2020
22020
Tunable Piezoresistive NEMS Pressure Sensor Simulation Under Various Environmental Conditions
N Kumar, A Gupta, P Singh, SC Mukhopadhyay
IEEE Sensors Letters, 2023
12023
Electro-Thermal Properties and Self-Heating Effect in Multi-Nanosheet FETs: Junctionless Mode Versus Inversion Mode
N Kumar, KK Bhinge, A Gupta, P Singh
7th IEEE Electron Devices Technology and Manufacturing (EDTM) Conference 2023, 2023
12023
Self-Heating Effect in Sub-5nm Node Junctionless Multi-Nanosheet FET
N Kumar, KK Bhinge, S Kumar, S Das, A Gupta, P Singh
6th IEEE International Conference on Emerging Electronics (ICEE) 2022, 2022
12022
Breakdown-Voltage Enhancing in LDMOS by Introducing Buffered Step Doping Technique
N Kumar, A Gupta, P Singh
2022 First International Conference on Electrical, Electronics, Information …, 2022
12022
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Articles 1–20