Massimo Poncino
Massimo Poncino
Professor, Computing Engineering
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A discrete-time battery model for high-level power estimation
L Benini, G Castelli, A Macii, E Macii, M Poncino, R Scarsi
Proceedings of the conference on Design, automation and test in Europe, 35-41, 2000
2012000
Discrete-time battery models for system-level low-power design
L Benini, G Castelli, A Macii, E Macii, M Poncino, R Scarsi
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9 (5), 630-640, 2001
1712001
SystemC cosimulation and emulation of multiprocessor SoC designs
L Benini, D Bertozzi, D Bruni, N Drago, F Fummi, M Poncino
Computer 36 (4), 53-59, 2003
1642003
Selective instruction compression for memory energy reduction in embedded systems
L Benini, A Macii, E Macii, M Poncino
Proceedings of the 1999 international symposium on Low power electronics and …, 1999
1421999
Architectures and synthesis algorithms for power-efficient bus interfaces
L Benini, A Macii, M Poncino, R Scarsi
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2000
1302000
Power optimization of core-based systems by address bus encoding
L Benini, G De Micheli, E Macii, M Poncino, S Quer
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 6 (4), 554-562, 1998
1281998
Wire placement for crosstalk energy minimization in address buses
L Macchiarulo, E Macii, M Poncino
Proceedings 2002 Design, Automation and Test in Europe Conference and …, 2002
1232002
System-level power optimization of special purpose applications: The beach solution
L Benini, G De Micheli, E Macii, M Poncino, S Quer
Proceedings of the 1997 international symposium on Low power electronics and …, 1997
1221997
Re-encoding sequential circuits to reduce power dissipation
GD Hachtel, M Hermida, A Pardo, M Poncino, F Somenzi
Proceedings of the 1994 IEEE/ACM international conference on Computer-aided …, 1994
1151994
Energy-aware design techniques for differential power analysis protection
L Benini, E Omerbegovic, A Macii, M Poncino, E Macii, F Pro
Proceedings 2003. Design Automation Conference (IEEE Cat. No. 03CH37451), 36-41, 2003
1142003
The human brain project and neuromorphic computing
A Calimera, E Macii, M Poncino
Functional neurology 28 (3), 191, 2013
1022013
NBTI-aware power gating for concurrent leakage and aging optimization
A Calimera, E Macii, M Poncino
Proceedings of the 2009 ACM/IEEE international symposium on Low power …, 2009
1022009
Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers
L Benini, G De Micheli, E Macii, M Poncino, R Scarsi
ACM Transactions on Design Automation of Electronic Systems (TODAES) 4 (4 …, 1999
1011999
Telescopic units: A new paradigm for performance optimization of VLSI designs
L Benini, E Macii, M Poncino, G De Micheli
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1998
1011998
Increasing energy efficiency of embedded systems by application-specific memory hierarchy generation
L Benini, A Macii, E Macii, M Poncino
IEEE Design & Test of Computers 17 (2), 74-85, 2000
972000
Layout-driven memory synthesis for embedded systems-on-chip
L Benini, L Macchiarulo, A Macii, M Poncino
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 10 (2), 96-105, 2002
962002
A recursive algorithm for low-power memory partitioning
L Benini, A Macii, M Poncino
Proceedings of the 2000 international symposium on Low power electronics and …, 2000
962000
Extending lifetime of portable systems by battery scheduling
L Benini, G Castelli, A Macii, E Macii, M Poncino, R Scarsi
Proceedings Design, Automation and Test in Europe. Conference and Exhibition …, 2001
922001
Design techniques for NBTI-tolerant power-gating architectures
A Calimera, E Macii, M Poncino
IEEE Transactions on Circuits and Systems II: Express Briefs 59 (4), 249-253, 2012
862012
Glitch power minimization by selective gate freezing
L Benini, G De Micheli, A Macii, E Macii, M Poncino, R Scarsi
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 8 (3), 287-298, 2000
842000
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