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Neethu K
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DoLaR: double layer routing for Bufferless mesh network-on-chip
RG Kunthara, K Neethu, RK James, SZ Sleeba, J Jose
TENCON 2019-2019 IEEE Region 10 Conference (TENCON), 400-405, 2019
52019
2L-2D Routing for Buffered Mesh Network-on-Chip
RG Kunthara, K Neethu, RK James, SZ Sleeba, TS Warrier, J Jose
VLSI Design and Test: 23rd International Symposium, VDAT 2019, Indore, India …, 2019
52019
Modelling and impact analysis of antipode attack in bufferless on-chip networks
RG Kunthara, VR Josna, K Neethu, RK James, J Jose
SN Computer Science 4 (3), 284, 2023
12023
Impact analysis of communication overhead in noc based dnn hardware accelerators
K Neethu, E Russo, RG Kunthara, RK James, J Jose
2022 IEEE 19th India Council International Conference (INDICON), 1-6, 2022
12022
RIBiT: Reduced Intra-flit Bit Transitions for Bufferless NoC
A Sarman, A Shaju, RG Kunthara, K Neethu, RK James, J Jose
2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration …, 2022
12022
Dual stage encoding technique to minimize cross coupling across noc links
SS Dev, SM Krishna, SS Archana, RG Kunthara, K Neethu, RK James
2021 25th International Symposium on VLSI Design and Test (VDAT), 1-6, 2021
12021
ELEMENT: Energy-efficient Multi-NoP Architecture for IMC-based 2.5 D Accelerator for DNN Training
K Neethu, KCS Shahana, RK James, J Jose, SK Mandal
IEEE Design & Test, 2023
2023
Interleaved Edge Routing in Buffered 3D Mesh & CMesh NoC
RG Kunthara, K Neethu, RK James, SZ Sleeba
2021 8th International Conference on Smart Computing and Communications …, 2021
2021
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