Maud Vinet
Maud Vinet
Quobly (ex CEA)
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Cited by
Cited by
A CMOS silicon spin qubit
R Maurand, X Jehl, D Kotekar-Patil, A Corna, H Bohuslavskyi, R Laviéville, ...
Nature communications 7 (1), 13575, 2016
Advances, challenges and opportunities in 3D CMOS sequential integration
P Batude, M Vinet, B Previtali, C Tabone, C Xu, J Mazurier, O Weber, ...
2011 International Electron Devices Meeting, 7.3. 1-7.3. 4, 2011
Advances in 3D CMOS sequential integration
P Batude, M Vinet, A Pouydebasque, C Le Royer, B Previtali, C Tabone, ...
2009 IEEE International Electron Devices Meeting (IEDM), 1-4, 2009
Single-donor ionization energies in a nanoscale CMOS channel
M Pierre, R Wacquez, X Jehl, M Sanquer, M Vinet, O Cueto
Nature nanotechnology 5 (2), 133-137, 2010
Planar Fully depleted SOI technology: A Powerful architecture for the 20nm node and beyond
O Faynot, F Andrieu, O Weber, C Fenouillet-Béranger, P Perreau, ...
2010 International Electron Devices Meeting, 3.2. 1-3.2. 4, 2010
3D monolithic integration: Technological challenges and electrical results
M Vinet, P Batude, C Tabone, B Previtali, C LeRoyer, A Pouydebasque, ...
Microelectronic Engineering 88 (4), 331-335, 2011
22nm FDSOI technology for emerging mobile, Internet-of-Things, and RF applications
R Carter, J Mazurier, L Pirro, JU Sachse, P Baars, J Faul, C Grass, ...
2016 IEEE International Electron Devices Meeting (IEDM), 2.2. 1-2.2. 4, 2016
Setting up 3D sequential integration for back-illuminated CMOS image sensors with highly miniaturized pixels with low temperature fully depleted SOI transistors
P Coudrain, P Batude, X Gagnard, C Leyris, S Ricq, M Vinet, ...
2008 IEEE International Electron Devices Meeting, 1-4, 2008
Demonstration of low temperature 3D sequential FDSOI integration down to 50 nm gate length
P Batude, M Vinet, C Xu, B Previtali, C Tabone, C Le Royer, L Sanchez, ...
2011 Symposium on VLSI Technology-Digest of Technical Papers, 158-159, 2011
3D monolithic integration
P Batude, M Vinet, A Pouydebasque, C Le Royer, B Previtali, C Tabone, ...
2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2233-2236, 2011
Circuit with transistors integrated in three dimensions and having a dynamically adjustable threshold voltage VT
P Batude, L Clavelier, MA Jaud, O Thomas, M Vinet
US Patent 8,183,630, 2012
Multi-UTBB FDSOI Device Architectures for Low-Power CMOS Circuit
JP Noel, O Thomas, MA Jaud, O Weber, T Poiroux, C Fenouillet-Beranger, ...
IEEE Transactions on Electron Devices 58 (8), 2473-2482, 2011
SRAM memory cell having transistors integrated at several levels and the threshold voltage VT of which is dynamically adjustable
O Thomas, P Batude, A Pouydebasque, M Vinet
US Patent 8,013,399, 2011
Germanium on Insulator and new 3D architectures opportunities for integration
M Vinet, C Le Royer, P Batude, JF Damlencourt, JM Hartmann, L Hutin, ...
International Journal of Nanotechnology 7 (4-8), 304-319, 2010
Integrated circuit with electrostatically coupled MOS transistors and method for producing such an integrated circuit
E Augendre, M Vinet, L Clavelier, P Batude
US Patent 8,853,785, 2014
Scaling silicon-based quantum computing using CMOS technology
MF Gonzalez-Zalba, S De Franceschi, E Charbon, T Meunier, M Vinet, ...
Nature Electronics 4 (12), 872-884, 2021
Multiple gate devices: advantages and challenges
T Poiroux, M Vinet, O Faynot, J Widiez, J Lolivier, T Ernst, B Previtali, ...
Microelectronic Engineering 80, 378-385, 2005
3DVLSI with CoolCube process: An alternative path to scaling
P Batude, C Fenouillet-Beranger, L Pasini, V Lu, F Deprat, L Brunet, ...
2015 Symposium on VLSI Technology (VLSI Technology), T48-T49, 2015
Bonded planar double-metal-gate NMOS transistors down to 10 nm
M Vinet, T Poiroux, J Widiez, J Lolivier, B Previtali, C Vizioz, B Guillaumot, ...
IEEE Electron Device Letters 26 (5), 317-319, 2005
Gate-reflectometry dispersive readout and coherent control of a spin qubit in silicon
A Crippa, R Ezzouch, A Aprá, A Amisse, R Lavieville, L Hutin, B Bertrand, ...
Nature communications 10 (1), 2776, 2019
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