| The EPFL combinational benchmark suite L Amarú, PE Gaillardon, G De Micheli Proceedings of the 24th International Workshop on Logic & Synthesis (IWLS), 2015 | 414 | 2015 |
| Majority-inverter graph: A new paradigm for logic optimization L Amaru, PE Gaillardon, G De Micheli IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015 | 244 | 2015 |
| Majority-inverter graph: A novel data-structure and algorithms for efficient logic optimization L Amarú, PE Gaillardon, G De Micheli Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014 | 218 | 2014 |
| The programmable logic-in-memory (PLiM) computer PE Gaillardon, L Amarú, A Siemon, E Linn, R Waser, A Chattopadhyay, ... 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 427-432, 2016 | 199 | 2016 |
| Exact synthesis of majority-inverter graphs and its applications M Soeken, LG Amaru, PE Gaillardon, G De Micheli IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 112 | 2017 |
| A successive cancellation decoder ASIC for a 1024-bit polar code in 180nm CMOS A Mishra, AJ Raymond, LG Amaru, G Sarkis, C Leroux, P Meinerzhagen, ... 2012 IEEE Asian solid state circuits conference (A-SSCC), 205-208, 2012 | 112 | 2012 |
| A novel basis for logic rewriting W Haaswijk, M Soeken, L Amarú, PE Gaillardon, G De Micheli 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 151-156, 2017 | 82 | 2017 |
| New logic synthesis as nanotechnology enabler L Amarú, PE Gaillardon, S Mitra, G De Micheli Proceedings of the IEEE 103 (11), 2168-2195, 2015 | 77 | 2015 |
| LSOracle: A logic synthesis framework driven by artificial intelligence WL Neto, M Austin, S Temple, L Amaru, X Tang, PE Gaillardon 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-6, 2019 | 71 | 2019 |
| High speed architectures for finding the first two maximum/minimum values LG Amaru, M Martina, G Masera IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20 (12 …, 2011 | 68 | 2011 |
| Design and benchmarking of hybrid CMOS-spin wave device circuits compared to 10nm CMOS O Zografos, B Sorée, A Vaysset, S Cosemans, L Amaru, PE Gaillardon, ... 2015 IEEE 15th International Conference on Nanotechnology (IEEE-NANO), 686-689, 2015 | 65 | 2015 |
| Reducing the multiplicative complexity in logic networks for cryptography and security applications E Testa, M Soeken, L Amarù, G De Micheli Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019 | 56 | 2019 |
| Boolean logic optimization in majority-inverter graphs L Amarú, PE Gaillardon, G De Micheli Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015 | 56* | 2015 |
| An MIG-based compiler for programmable logic-in-memory architectures M Soeken, S Shirinzadeh, PE Gaillardon, LG Amarú, R Drechsler, ... Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 50 | 2016 |
| Advanced system on a chip design based on controllable-polarity FETs PE Gaillardon, L Amaru, J Zhang, G De Micheli 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014 | 50 | 2014 |
| A Sound and Complete Axiomatization of Majority- Logic L Amarú, PE Gaillardon, A Chattopadhyay, G De Micheli IEEE Transactions on Computers 65 (9), 2889-2895, 2015 | 47 | 2015 |
| BDS-MAJ: a BDD-based logic synthesis tool exploiting majority logic decomposition. LG Amarù, PE Gaillardon, G De Micheli 50th Design Automation Conference (DAC 2013), Austin, Texas (USA)., 2013 | 47 | 2013 |
| Scalable generic logic synthesis: One approach to rule them all H Riener, E Testa, W Haaswijk, A Mishchenko, L Amarù, G De Micheli, ... Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019 | 46 | 2019 |
| Biconditional BDD: A novel canonical BDD for logic synthesis targeting XOR-rich circuits L Amarú, PE Gaillardon, G De Micheli 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2013 | 46 | 2013 |
| Power-Gated Differential Logic Style Based on Double-Gate Controllable Polarity Transistors L Amaru, PE Gaillardon, J Zhang, GD Micheli IEEE Transactions on Circuits and Systems II: Express Briefs, 2013 | 43 | 2013 |
Giovanni De MicheliEPFL, StanfordVerified email at epfl.ch
