Follow
Luca Amar¨
Title
Cited by
Cited by
Year
The EPFL combinational benchmark suite
L Amar˙, PE Gaillardon, G De Micheli
Proceedings of the 24th International Workshop on Logic & Synthesis (IWLS), 2015
3342015
Majority-inverter graph: A new paradigm for logic optimization
L Amaru, PE Gaillardon, G De Micheli
IEEE Transactions on Computer-Aided Design of Integrated Circuits andá…, 2015
2252015
Majority-inverter graph: A novel data-structure and algorithms for efficient logic optimization
L Amar˙, PE Gaillardon, G De Micheli
Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014
2122014
The programmable logic-in-memory (PLiM) computer
PE Gaillardon, L Amar˙, A Siemon, E Linn, R Waser, A Chattopadhyay, ...
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 427-432, 2016
1892016
A successive cancellation decoder ASIC for a 1024-bit polar code in 180nm CMOS
A Mishra, AJ Raymond, LG Amaru, G Sarkis, C Leroux, P Meinerzhagen, ...
2012 IEEE Asian solid state circuits conference (A-SSCC), 205-208, 2012
1112012
Exact synthesis of majority-inverter graphs and its applications
M Soeken, LG Amaru, PE Gaillardon, G De Micheli
IEEE Transactions on Computer-Aided Design of Integrated Circuits andá…, 2017
1052017
A novel basis for logic rewriting
W Haaswijk, M Soeken, L Amar˙, PE Gaillardon, G De Micheli
2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 151-156, 2017
742017
New logic synthesis as nanotechnology enabler
L Amar˙, PE Gaillardon, S Mitra, G De Micheli
Proceedings of the IEEE 103 (11), 2168-2195, 2015
732015
High speed architectures for finding the first two maximum/minimum values
LG Amaru, M Martina, G Masera
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20 (12á…, 2011
662011
Design and benchmarking of hybrid CMOS-spin wave device circuits compared to 10nm CMOS
O Zografos, B SorÚe, A Vaysset, S Cosemans, L Amaru, PE Gaillardon, ...
2015 IEEE 15th International Conference on Nanotechnology (IEEE-NANO), 686-689, 2015
612015
LSOracle: A logic synthesis framework driven by artificial intelligence
WL Neto, M Austin, S Temple, L Amaru, X Tang, PE Gaillardon
2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-6, 2019
592019
Advanced system on a chip design based on controllable-polarity FETs
PE Gaillardon, L Amaru, J Zhang, G De Micheli
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014
512014
An MIG-based compiler for programmable logic-in-memory architectures
M Soeken, S Shirinzadeh, PE Gaillardon, LG Amar˙, R Drechsler, ...
Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016
472016
A Sound and Complete Axiomatization of Majority- Logic
L Amar˙, PE Gaillardon, A Chattopadhyay, G De Micheli
IEEE Transactions on Computers 65 (9), 2889-2895, 2015
472015
Boolean logic optimization in majority-inverter graphs
L Amar˙, PE Gaillardon, G De Micheli
Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015
472015
BDS-MAJ: a BDD-based logic synthesis tool exploiting majority logic decomposition.
LG Amar¨, PE Gaillardon, G De Micheli
50th Design Automation Conference (DAC 2013), Austin, Texas (USA)., 2013
472013
Biconditional BDD: A novel canonical BDD for logic synthesis targeting XOR-rich circuits
L Amar˙, PE Gaillardon, G De Micheli
2013 Design, Automation & Test in Europe Conference & Exhibition (DATEá…, 2013
452013
Reducing the multiplicative complexity in logic networks for cryptography and security applications
E Testa, M Soeken, L Amar¨, G De Micheli
Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019
442019
Power-Gated Differential Logic Style Based on Double-Gate Controllable Polarity Transistors
L Amaru, PE Gaillardon, J Zhang, GD Micheli
IEEE Transactions on Circuits and Systems II: Express Briefs, 2013
432013
Logic synthesis for established and emerging computing
E Testa, M Soeken, LG Amar, G De Micheli
Proceedings of the IEEE 107 (1), 165-184, 2018
402018
The system can't perform the operation now. Try again later.
Articles 1–20