| A unified clock and switched-capacitor-based power delivery architecture for variation tolerance in low-voltage SoC domains F ur Rahman, S Kim, N John, R Kumar, X Li, R Pamula, KA Bowman, ... IEEE Journal of Solid-State Circuits 54 (4), 1173-1184, 2019 | 26 | 2019 |
| A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0 V cortex-M0 processor X Sun, S Kim, F ur Rahman, VR Pamula, X Li, N John, VS Sathe 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 302-304, 2018 | 15 | 2018 |
| An All-Digital Fused PLL-Buck Architecture for 82% Average Vdd-Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor X Sun, F ur Rahman, VR Pamula, S Kim, X Li, N John, VS Sathe IEEE Journal of Solid-State Circuits 54 (11), 3215-3225, 2019 | 13 | 2019 |
| An all-digital unified clock frequency and switched-capacitor voltage regulator for variation tolerance in a sub-threshold ARM cortex M0 processor FU Rahman, S Kim, N John, R Kumar, X Li, R Pamula, KA Bowman, ... 2018 IEEE Symposium on VLSI Circuits, 65-66, 2018 | 13 | 2018 |
| Electrical circuit design using cells with metal lines RB Lefferts, J Naveen, LJH Alves, J Amanda, N Gopalan, ... US Patent 11,334,705, 2022 | | 2022 |
