Pieter Schuddinck
Pieter Schuddinck
High-Density Logic Technology DTCO researcher
Verified email at
Cited by
Cited by
Device exploration of nanosheet transistors for sub-7-nm technology node
D Jang, D Yakimets, G Eneman, P Schuddinck, MG Bardon, P Raghavan, ...
IEEE Transactions on Electron Devices 64 (6), 2707-2713, 2017
Vertical GAAFETs for the ultimate CMOS scaling
D Yakimets, G Eneman, P Schuddinck, TH Bao, MG Bardon, P Raghavan, ...
IEEE Transactions on Electron Devices 62 (5), 1433-1439, 2015
The Complementary FET (CFET) for CMOS scaling beyond N3
J Ryckaert, P Schuddinck, P Weckx, G Bouche, B Vincent, J Smith, ...
2018 IEEE Symposium on Vlsi Technology, 141-142, 2018
Understanding energy efficiency benefits of carbon nanotube field-effect transistors for digital VLSI
G Hills, MG Bardon, G Doornbos, D Yakimets, P Schuddinck, R Baert, ...
IEEE Transactions on Nanotechnology 17 (6), 1259-1269, 2018
Power aware FinFET and lateral nanosheet FET targeting for 3nm CMOS technology
D Yakimets, MG Bardon, D Jang, P Schuddinck, Y Sherazi, P Weckx, ...
2017 IEEE International Electron Devices Meeting (IEDM), 20.4. 1-20.4. 4, 2017
Novel forksheet device architecture as ultimate logic scaling device towards 2nm
P Weckx, J Ryckaert, ED Litta, D Yakimets, P Matagne, P Schuddinck, ...
2019 IEEE International Electron Devices Meeting (IEDM), 36.5. 1-36.5. 4, 2019
Extreme scaling enabled by 5 tracks cells: Holistic design-device co-optimization for FinFETs and lateral nanowires
MG Bardon, Y Sherazi, P Schuddinck, D Jang, D Yakimets, P Debacker, ...
2016 IEEE International Electron Devices Meeting (IEDM), 28.2. 1-28.2. 4, 2016
Enabling sub-5nm CMOS technology scaling thinner and taller!
J Ryckaert, MH Na, P Weckx, D Jang, P Schuddinck, B Chehab, S Patli, ...
2019 IEEE International Electron Devices Meeting (IEDM), 29.4. 1-29.4. 4, 2019
First monolithic integration of 3d complementary fet (cfet) on 300mm wafers
S Subramanian, M Hosseini, T Chiarella, S Sarkar, P Schuddinck, ...
2020 Ieee Symposium on Vlsi Technology, 1-2, 2020
Vertical device architecture for 5nm and beyond: device & circuit implications
AVY Thean, D Yakimets, TH Bao, P Schuddinck, S Sakhare, MG Bardon, ...
2015 Symposium on VLSI Technology (VLSI Technology), T26-T27, 2015
Holisitic device exploration for 7nm node
P Raghavan, MG Bardon, D Jang, P Schuddinck, D Yakimets, J Ryckaert, ...
2015 IEEE Custom Integrated Circuits Conference (CICC), 1-5, 2015
Stacked nanosheet fork architecture for SRAM design and device co-optimization toward 3nm
P Weckx, J Ryckaert, V Putcha, A De Keersgieter, J Boemmels, ...
2017 IEEE International Electron Devices Meeting (IEDM), 20.5. 1-20.5. 4, 2017
Device-, circuit-& block-level evaluation of CFET in a 4 track library
P Schuddinck, O Zografos, P Weckx, P Matagne, S Sarkar, Y Sherazi, ...
2019 Symposium on VLSI Technology, T204-T205, 2019
Power-performance trade-offs for lateral nanosheets on ultra-scaled standard cells
MG Bardon, Y Sherazi, D Jang, D Yakimets, P Schuddinck, R Baert, ...
2018 IEEE Symposium on VLSI Technology, 143-144, 2018
Dimensioning for power and performance under 10nm: The limits of FinFETs scaling
MG Bardon, P Schuddinck, P Raghavan, D Jang, D Yakimets, A Mercha, ...
2015 International Conference on IC Design & Technology (ICICDT), 1-4, 2015
Layout-induced stress effects in 14nm & 10nm FinFETs and their impact on performance
MG Bardon, V Moroz, G Eneman, P Schuddinck, M Dehan, D Yakimets, ...
2013 Symposium on VLSI Technology, T114-T115, 2013
DTCO at N7 and beyond: patterning and electrical compromises and opportunities
J Ryckaert, P Raghavan, P Schuddinck, HB Trong, A Mallik, SS Sakhare, ...
Design-Process-Technology Co-optimization for Manufacturability IX 9427, 101-108, 2015
Introducing 2D-FETs in device scaling roadmap using DTCO
Z Ahmed, A Afzalian, T Schram, D Jang, D Verreck, Q Smets, ...
2020 IEEE International Electron Devices Meeting (IEDM), 22.5. 1-22.5. 4, 2020
Low track height standard cell design in iN7 using scaling boosters
SMY Sherazi, C Jha, D Rodopoulos, P Debacker, B Chava, L Matti, ...
Design-Process-Technology Co-optimization for Manufacturability XI 10148 …, 2017
Design technology co-optimization for N10
J Ryckaert, P Raghavan, R Baert, MG Bardon, M Dusa, A Mallik, ...
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 1-8, 2014
The system can't perform the operation now. Try again later.
Articles 1–20