Tomasz Talaśka
Tomasz Talaśka
UTP Univeristy of Technology and Life Sciences
Verified email at utp.edu.pl
Title
Cited by
Cited by
Year
Realization of the conscience mechanism in CMOS implementation of winner-takes-all self-organizing neural networks
R Długosz, T Talaśka, W Pedrycz, R Wojtyna
IEEE Transactions on Neural Networks 21 (6), 961-971, 2010
772010
Current-mode analog adaptive mechanism for ultra-low-power neural networks
R Długosz, T Talaśka, W Pedrycz
IEEE Transactions on Circuits and Systems II: Express Briefs 58 (1), 31-35, 2011
452011
Low power current-mode binary-tree asynchronous Min/Max circuit
RŁ DŁugosz, T Talaśka
Microelectronics Journal 41 (1), 64-73, 2010
282010
Analog programmable distance calculation circuit for winner takes all neural network realized in the CMOS technology
T Talaśka, M Kolasa, R Długosz, W Pedrycz
Ieee transactions on neural networks and learning systems 27 (3), 661-673, 2015
272015
Transresistance CMOS neuron for adaptive neural networks implemented in hardware
R Wojtyna, T Talaśka
BULLETIN OF THE POLISH ACADEMY OF SCIENCES, TECHNICAL SCIENCES 54 (4), 2006
222006
Adaptive Weight Change Mechanism for Kohonens's Neural Network Implemented in CMOS 0.18 μm Technology
T Talaśka, R Długosz, W Pedrycz
European Symposium on Artificial Neural Networks (ESANN), 151-156, 2007
212007
New binary-tree-based Winner-Takes-All circuit for learning on silicon Kohonen's networks
R Długosz, T Talaśka, R Wojtyna
International Conference On Signals And Electronic Systems (ICSES), 441-446, 2006
182006
Current mode analog Kohonen neural network
T Talaska, R Dlugosz, R Wojtyna
2007 14th International Conference on Mixed Design of Integrated Circuits …, 2007
16*2007
Experimental Kohonen neural network implemented in CMOS 0.18 μm technology
R Długosz, T Talaśka, J Dalecki, R Wojtyna
International Conference Mixed Design of Integrated Circuits and Systems …, 2008
142008
Initialization mechanism in Kohonen neural network implemented in CMOS technology
T Talaśka, R Długosz
European Symposium on Artificial Neural Networks (ESANN), 337-342, 2008
112008
An efficient initialization mechanism of neurons for Winner Takes All Neural Network implemented in the CMOS technology
T Talaśka, M Kolasa, R Długosz, PA Farine
Applied Mathematics and Computation 267, 119-138, 2015
102015
Current Mode Euclidean Distance Calculation Circuit for Kohonen's Neural Network Implemented in CMOS 0.18 µm Technology
T Talaśka, R Długosz
Canadian Conference on Electrical and Computer Engineering (CCECE), 437-440, 2007
102007
Implementation Of The Conscience Mechanism For Kohonen's Neural Network In Cmos 0.18 μm Technology
T Talaśka, R Wojtyna, R Długosz, K Iniewski
International Conference Mixed Design of Integrated Circuits and Systems …, 2006
10*2006
Analog-Counter-Based Conscience Mechanism in Kohonen's Neural Network Implemented in CMOS 0.18 μm Technology
T Talaśka, R Wojtyna, R Długosz, K Iniewski, W Pedrycz
IEEE Workshop on Signal Processing Systems Design and Implementation (SIPS …, 2006
102006
Adaptive Weight Change Mechanism for Kohonens's Neural Network Implemented in CMOS 0.18 μm Technology
T Talaska, RT Dlugosz, W Pedrycz
Proceedings of the European Symposium on Artificial Neural Networks (ESANN …, 2007
82007
Design and optimization of hardware-efficient filters for active safety algorithms
RT Dlugosz, M Szulc, M Kolasa, P Skruch, K Kogut, P Markiewicz, ...
SAE International Journal of Passenger Cars-Electronic and Electrical …, 2015
72015
Improved power-saving synapse for hardware implemented ANN’s
R Wojtyna, T Talaska
Int. Conf. on Signals and Electronic Systems ICSES 4, 27-30, 2004
72004
Improved power-saving synapse for adaptive neuroprocessing on silicon
R Wojtyna, T Talaska
International conference on signals and electronic systems, 27-30, 2004
72004
Components of Artificial Neural Networks Realized in CMOS Technology to be Used in Intelligent Sensors in Wireless Sensor Networks
T Talaśka
Sensors 18 (12), 4499, 2018
62018
Analog, parallel, sorting circuit for the application in Neural Gas learning algorithm implemented in the CMOS technology
T Talaśka, R Długosz
Applied Mathematics and Computation 319, 218-235, 2018
62018
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Articles 1–20