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Guillermo PayŠ-VayŠ
Guillermo PayŠ-VayŠ
Professor, Technische Universitšt Braunschweig, L3S Research Center
Verified email at tu-braunschweig.de - Homepage
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Cited by
Cited by
Year
Transport-triggered soft cores
P Jššskelšinen, A Tervo, GP VayŠ, T Viitanen, N Behmann, J Takala, ...
2018 IEEE International Parallel and Distributed Processing Symposium†…, 2018
262018
Performance monitoring for automatic speech recognition in noisy multi-channel environments
BT Meyer, SH Mallidi, AMC Martinez, G PayŠ-VayŠ, H Kayser, ...
2016 IEEE Spoken Language Technology Workshop (SLT), 50-56, 2016
212016
DNN-based performance measures for predicting error rates in automatic speech recognition and optimizing hearing aid parameters
AMC Martinez, L Gerlach, G PayŠ-VayŠ, H Hermansky, J Ooster, ...
Speech Communication 106, 44-56, 2019
202019
A fair comparison of adders in stochastic regime
A Najafi, M WeiŖbrich, GP VayŠ, A Garcia-Ortiz
2017 27th International Symposium on Power and Timing Modeling, Optimization†…, 2017
202017
Coherent design of hybrid approximate adders: Unified design framework and metrics
A Najafi, M WeiŖbrich, G PayŠ-VayŠ, A Garcia-Ortiz
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 8 (4†…, 2018
192018
VLIW architecture optimization for an efficient computation of stereoscopic video applications
G PayŠ-VayŠ, J MartŪn-Langerwerf, C Banz, F Giesemann, P Pirsch, ...
The 2010 International Conference on Green Circuits and Systems, 457-462, 2010
192010
Customizing a vliw-simd application-specific instruction-set processor for hearing aid devices
J Hartig, L Gerlach, G PayŠ-VayŠ, H Blume
2014 IEEE Workshop on Signal Processing Systems (SiPS), 1-6, 2014
162014
An area efficient real-and complex-valued multiply-accumulate SIMD unit for digital signal processors
L Gerlach, G PayŠ-VayŠ, H Blume
2015 IEEE Workshop on Signal Processing Systems (SiPS), 1-6, 2015
142015
2D-DCT on FPGA by polynomial transformation in two-dimensions
AM Patino, MM Peirů, F Ballester, G Paya
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No†…, 2004
132004
A survey on application specific processor architectures for digital hearing aids
L Gerlach, G Paya-Vaya, H Blume
Journal of Signal Processing Systems, 1-16, 2021
122021
Dynamic data-path self-reconfiguration of a VLIW-SIMD soft-processor architecture
G PayŠ-VayŠ, R Burg, H Blume
Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 26, 2012
122012
Design space exploration of media processors: A parameterized scheduler
G Paya-Vaya, J Martin-Langerwerf, P Taptimthong, P Pirsch
2007 international conference on embedded computer systems: Architectures†…, 2007
122007
FLINT: Layout-oriented FPGA-based methodology for fault tolerant ASIC design
R Nowosielski, L Gerlach, S Bieband, G PayŠ-VayŠ, H Blume
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 297-300, 2015
112015
Performance evaluation of the Intel Xeon Phi manycore architecture using parallel video-based driver assistance algorithms
OJ Arndt, D Becker, F Giesemann, G PayŠ-VayŠ, C Bartels, H Blume
2014 International Conference on Embedded Computer Systems: Architectures†…, 2014
112014
Design and analysis of a generic VLIW processor for multimedia applications
G PayŠ-VayŠ
Diss. Institute of Microelectronic Systems, Leibniz Universitšt Hannover, 2011
112011
A multi-shared register file structure for VLIW processors
G PayŠ-VayŠ, J MartŪn-Langerwerf, P Pirsch
Journal of Signal Processing Systems 58, 215-231, 2010
112010
Using a genetic algorithm approach to reduce register file pressure during instruction scheduling
F Giesemann, G PayŠ-VayŠ, L Gerlach, H Blume, F Pflug, G von Voigt
2017 International Conference on Embedded Computer Systems: Architectures†…, 2017
102017
Towards a common software/hardware methodology for future advanced driver assistance systems
G PayŠ-VayŠ, H Blume
Taylor & Francis, 2017
102017
ASEV—Automatic situation assessment for event-driven video analysis
M Fenzi, J Ostermann, N Mentzer, G PayŠ-VayŠ, H Blume, TN Nguyen, ...
2014 11th IEEE international conference on advanced video and signal based†…, 2014
102014
Instruction merging to increase parallelism in VLIW architectures
G PayŠ-VayŠ, J MartŪn-Langerwerf, F Giesemann, H Blume, P Pirsch
2009 International Symposium on System-on-Chip, 143-146, 2009
102009
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