Pieter Weckx
Pieter Weckx
R&D Manager imec
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Cited by
Cited by
Comphy—A compact-physics framework for unified modeling of BTI
G Rzepa, J Franco, B O’Sullivan, A Subirats, M Simicic, G Hellings, ...
Microelectronics Reliability 85, 49-65, 2018
The Complementary FET (CFET) for CMOS scaling beyond N3
J Ryckaert, P Schuddinck, P Weckx, G Bouche, B Vincent, J Smith, ...
2018 IEEE Symposium on Vlsi Technology, 141-142, 2018
Power aware FinFET and lateral nanosheet FET targeting for 3nm CMOS technology
D Yakimets, MG Bardon, D Jang, P Schuddinck, Y Sherazi, P Weckx, ...
2017 IEEE International Electron Devices Meeting (IEDM), 20.4. 1-20.4. 4, 2017
Novel forksheet device architecture as ultimate logic scaling device towards 2nm
P Weckx, J Ryckaert, ED Litta, D Yakimets, P Matagne, P Schuddinck, ...
2019 IEEE International Electron Devices Meeting (IEDM), 36.5. 1-36.5. 4, 2019
Comparison of reaction-diffusion and atomistic trap-based BTI models for logic gates
H Kükner, S Khan, P Weckx, P Raghavan, S Hamdioui, B Kaczer, ...
IEEE transactions on device and materials reliability 14 (1), 182-193, 2013
Enabling sub-5nm CMOS technology scaling thinner and taller!
J Ryckaert, MH Na, P Weckx, D Jang, P Schuddinck, B Chehab, S Patli, ...
2019 IEEE International Electron Devices Meeting (IEDM), 29.4. 1-29.4. 4, 2019
Defect-based methodology for workload-dependent circuit lifetime projections-Application to SRAM
P Weckx, B Kaczer, M Toledano-Luque, T Grasser, PJ Roussel, H Kukner, ...
2013 IEEE International Reliability Physics Symposium (IRPS), 3A. 4.1-3A. 4.7, 2013
Degradation of time dependent variability due to interface state generation
M Toledano-Luque, B Kaczer, J Franco, PJ Roussel, M Bina, T Grasser, ...
2013 Symposium on VLSI Technology, T190-T191, 2013
A brief overview of gate oxide defect properties and their relation to MOSFET instabilities and device and circuit time-dependent variability
B Kaczer, J Franco, P Weckx, PJ Roussel, V Putcha, E Bury, M Simicic, ...
Microelectronics Reliability 81, 186-194, 2018
The impact of sequential-3D integration on semiconductor scaling roadmap
A Mallik, A Vandooren, L Witters, A Walke, J Franco, Y Sherazi, P Weckx, ...
2017 IEEE International Electron Devices Meeting (IEDM), 32.1. 1-31.1. 4, 2017
Forksheet FETs for advanced CMOS scaling: forksheet-nanosheet co-integration and dual work function metal gates at 17nm NP space
H Mertens, R Ritzenthaler, Y Oniki, B Briggs, BT Chan, A Hikavyy, T Hopf, ...
2021 Symposium on VLSI Technology, 1-2, 2021
Implications of BTI-induced time-dependent statistics on yield estimation of digital circuits
P Weckx, B Kaczer, M Toledano-Luque, P Raghavan, J Franco, ...
IEEE Transactions on Electron Devices 61 (3), 666-673, 2014
Stacked nanosheet fork architecture for SRAM design and device co-optimization toward 3nm
P Weckx, J Ryckaert, V Putcha, A De Keersgieter, J Boemmels, ...
2017 IEEE International Electron Devices Meeting (IEDM), 20.5. 1-20.5. 4, 2017
Characterization of time-dependent variability using 32k transistor arrays in an advanced HK/MG technology
P Weckx, B Kaczer, C Chen, J Franco, E Bury, K Chanda, J Watt, ...
2015 IEEE International Reliability Physics Symposium, 3B. 1.1-3B. 1.6, 2015
Enabling CMOS scaling towards 3nm and beyond
A Mocuta, P Weckx, S Demuynck, D Radisic, Y Oniki, J Ryckaert
2018 IEEE Symposium on VLSI Technology, 147-148, 2018
Device-, circuit-& block-level evaluation of CFET in a 4 track library
P Schuddinck, O Zografos, P Weckx, P Matagne, S Sarkar, Y Sherazi, ...
2019 Symposium on VLSI Technology, T204-T205, 2019
Integral impact of BTI, PVT variation, and workload on SRAM sense amplifier
I Agbo, M Taouil, D Kraak, S Hamdioui, H Kükner, P Weckx, P Raghavan, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (4 …, 2017
Origins and implications of increased channel hot carrier variability in nFinFETs
B Kaczer, J Franco, M Cho, T Grasser, PJ Roussel, S Tyaginov, M Bina, ...
2015 IEEE International Reliability Physics Symposium, 3B. 5.1-3B. 5.6, 2015
Quantitative and predictive model of reading current variability in deeply scaled vertical poly-Si channel for 3D memories
M Toledano-Luque, R Degraeve, B Kaczer, B Tang, PJ Roussel, P Weckx, ...
2012 International Electron Devices Meeting, 9.2. 1-9.2. 4, 2012
Atomistic pseudo-transient BTI simulation with inherent workload memory
D Rodopoulos, P Weckx, M Noltsis, F Catthoor, D Soudris
IEEE Transactions on Device and Materials Reliability 14 (2), 704-714, 2014
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