| Memristor-based low-power high-speed nonvolatile hybrid memory array design KA Faruque, BR Biswas, ABMH Rashid Circuits, Systems, and Signal Processing 36, 3585-3597, 2017 | 14 | 2017 |
| A data erasing writing technique based 1t1m quaternary memory circuit design BR Biswas, ABM Harun-Ur-Rashid 2018 10th International Conference on Electrical and Computer Engineering …, 2018 | 8 | 2018 |
| Memristor-Specific Failures: New Verification Methods and Emerging Test Problems BR Biswas, S Gupta 2022 IEEE 40th VLSI Test Symposium (VTS), 1-7, 2022 | 1 | 2022 |
| Systematic Generation of Memristor-Transistor Single-Phase Combinational Logic Cells BR Biswas, C Yuan, F Wang, S Gupta IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024 | | 2024 |
| Development of Simulation Model of a Controlled Rectifier for Reactive Power Compensation BR Biswas, R Das, MA Abedin, ABM Harun-Ur-Rashid 2018 10th International Conference on Electrical and Computer Engineering …, 2018 | | 2018 |
| Design of non-volatile quaternary memory cell using memristor-mos hybrid structure BR Biswas Department of Electrical and Electronic Engineering (EEE), BUET, 2018 | | 2018 |
| A novel low buffered optimized Solid State Drive controller R Das, BR Biswas, ABMH Rashid, MA Abedin 2016 9th International Conference on Electrical and Computer Engineering …, 2016 | | 2016 |
ABM Harun-ur RashidProfessorVerified email at eee.buet.ac.bd
